The present invention generally relates to a semiconductor device having a multilevel interconnect structure and a method for fabricating the same, and more particularly relates to techniques for reducing wiring delay.
Currently, the size of a transistor goes on being decreased day by day. It has already been shown that, in transistors for silicon LSI""s belonging to the size generation of 0.07 xcexcm or more, in particular, if 1/k scaling is realized in the lateral direction, the speed thereof can be increased by 1/k.
On the other hand, in multilevel interconnect technology, the contribution of wire-to-wire capacitance is significant if the sizes belong to the generation of about 0.5 xcexcm or more. Thus, it has already been shown that even if 1/k scaling is realized in the lateral direction, the wiring delay thereof is reduced by no more than 1/k2xe2x88x92a, where a is a coefficient having a value from 1 to 2.
In view of the state in the art, a scaling rule for reducing the wiring delay by approximately the same degree as 1/k was suggested. In accordance with the scaling rule, the thickness of a wire is scaled down to 1/k⅔, the thickness of an interlayer dielectric film to 1/kxc2xd, the relative dielectric constant of the interlayer dielectric film to 1/k⅓ and the specific resistance of the wire to 1/k⅓. However, if this scaling rule must be obeyed, the relative dielectric constants of materials for an interlayer dielectric film should be decreased to be 3.5, 3.1, 2.8, 2.4 and 1.9 for the 0.35 xcexcm-generation, 0.25 xcexcm-generation, 0.18 xcexcm-generation, 0.13 xcexcm-generation and 0.10 xcexcm-generation, respectively.
The relative dielectric constant of a silicon dioxide film, which is widely used as an interlayer dielectric film, is about 4. Thus, so long as this scaling rule must be complied with, a silicon dioxide film can no longer be applied for the generations of 0.35 xcexcm or less. Among various organic low-dielectric-constant films under development, an HSQ film (2.2), a Teflon-AF film (1.9) and the like have smallest dielectric constants. If the air having a relative dielectric constant of 1 could be used as an alternative to an insulating film, then the speed of a CMOS device with a design rule of 0.35 xcexcm could be further increased by about 33% as compared with the case of using an HSQ film, for example.
Accordingly, it is considered that the above described various problems might be solved by employing a gas-dielectric interconnect process for disposing wires between the wire-to-wire gaps filled with a gas.
Hereinafter, an exemplary application of a gas-dielectric interconnect process for trench interconnection (suggested by M. B. Anand et al., VLSI Symposium 1996, p. 82) will be described with reference to the drawings.
FIGS. 10(a) and 10(b) are cross-sectional views illustrating a conventional single-damascene gas-dielectric interconnect process, while FIG. 10(c) is a process flow chart thereof. FIGS. 11(a) and 11(b) are cross-sectional views illustrating a conventional dual-damascene gas-dielectric interconnect process, while FIG. 11(c) is a process flow chart thereof. The two types of semiconductor device structures to be formed in accordance with the respective processes will be described below with reference to the process flow charts of FIGS. 10(c) and 11(c).
First, the single-damascene gas-dielectric interconnect process will be described. In the process step shown in FIG. 10(a), a carbon film 102 is formed on a substrate 101 by sputtering, and trenches are formed in the carbon film 102. Then, a metal film is deposited over the entire surface of the substrate and etched-back, thereby forming a metal interconnect layer 103 so as to fill in the trenches.
Next, in the process step shown in FIG. 10(b), a thin silicon dioxide film 104 is formed over the substrate and then the carbon film 102 is burned to be ashed in a furnace at a temperature from 400xc2x0 C. to 450xc2x0 C. while supplying O2 gas thereto. As a result, the gaps between the wires in the interconnect layer 103 form a gas layer 105.
Then, a carbon film is deposited over the entire surface of the substrate and a metal film is deposited so as to fill in the via-holes formed in the carbon film, thereby forming plugs to be connected to the respective wires. Thereafter, the process returns to the step shown in FIG. 10(a) and a similar process is repeatedly performed to remove the surrounding carbon film.
In this way, by repeatedly performing the process steps shown in FIGS. 10(a) and 10(b) and the subsequent process step of forming plugs, a gas-dielectric interconnect structure, in which gas layers exist between multilevel interconnects, can be formed.
On the other hand, the dual-damascene gas-dielectric interconnect process is performed in the following manner.
At the outset of the process step shown in FIG. 11(a), the steps shown in FIGS. 10(a) and 10(b) have already been performed to form the (lower) interconnect layer 103, in which wires are surrounded by the gas layer 105, and the (lower) silicon dioxide film 104 on the substrate 101. In such a state, a carbon film 106 is formed by sputtering over the entire surface of the substrate, a thin silicon dioxide film 107 is deposited thereon, and another carbon film 108 is further deposited thereon. Then, trenches are formed through the carbon film 108 and via-holes are formed through the silicon dioxide film 107 and the carbon film 106. Thereafter, a metal film is deposited over the entire surface of the substrate and etched-back, thereby forming metal plugs 109 and an upper metal interconnect layer 110 so as to fill in the via-holes and the trenches simultaneously.
Next, in the process step shown in FIG. 11(b), a thin silicon dioxide film 111 is formed over the substrate and the two carbon films 106 and 108 are burned to be ashed at a temperature from 400xc2x0 C. to 450xc2x0 C. while supplying O2 gas thereto. As a result, gas layers 113 and 114 are formed to surround the plugs 109 and the wires in the upper interconnect layer 110.
That is to say, by interposing gas layers as alternatives to low-dielectric-constant films, a multilevel interconnect structure contributing to the reduction of parasitic capacitance is formed.
However, in accordance with the processes shown in FIGS. 10(a) and 10(b) and FIGS. 11(a) and 11(b), the thicknesses of the silicon dioxide films 104, 107, 111 should be sufficiently small such that oxygen can be sequentially permeated downward during ashing and removal of the carbon films 102, 106, 108 within an oxygen ambient at about 450xc2x0 C. in the process steps shown in FIGS. 10(b) and 11(b). Then, the silicon dioxide films cannot show sufficient strength for supporting the respective wires, and therefore the reliability is adversely deteriorated.
In addition, the procedures of repeatedly depositing carbon films, silicon dioxide films and metal films and repeatedly ashing the carbon films to be removed are so complicated that the process efficiency is unsatisfactory.
On the other hand, in order to reduce the specific resistance of a wire and thereby reduce the wiring delay, it is considered that Cu wires should naturally replace Al wires. However, since it is difficult to form Cu wires by dry etching, the steps shown in FIGS. 10(a) and 10(b) and FIGS. 11(a) and 11(b), in which trenches and holes are formed beforehand and then Cu is filled therein, have been taken. As a specific alternative procedure of such a method, a reflow process, in which a Cu film is deposited by sputtering and then made to flow and injected into trenches and holes within a hydrogen ambient at a temperature from 400 to 500xc2x0 C., is now under development and expected to be used widely. However, since a currently developed a low-dielectric-constant film (e.g., a film having a relative dielectric constant of 2.8 or less) has thermal resistance as low as 400xc2x0 C. or less, the low-dielectric-constant film itself possibly flows. Thus, it is difficult to use such a film with the reflow technology for forming Cu wires. That is to say, the reduction in resistance of wires is undesirably limited by the thermal resistance of such a low-dielectric-constant film.
In view of the above-described problems, the present invention was made to accomplish a primary object of providing a highly reliable semiconductor device with the strength of the interconnect structure thereof enhanced, and a method for efficiently fabricating such a semiconductor device while utilizing fundamental techniques for forming a gas-dielectric interconnect structure.
A secondary object of the present invention is providing a semiconductor device having an interconnect structure that uses a low-dielectric-constant film having low thermal resistance as an interlayer dielectric film and still can sufficiently resist to a heat treatment required for forming trench-filling wires having low resistance, and a method for fabricating the same.
A first semiconductor device according to the present invention includes: a semiconductor substrate; a plurality of interconnect layers disposed at respectively different levels above the semiconductor substrate, each said interconnect layer including a plurality of wires; a plurality of plugs, each said plug vertically connecting an associated wire in one of the interconnect layers to the semiconductor substrate or vertically connecting a pair of wires to each other, the pair of wires belonging to two mutually different ones of the interconnect layers; a plurality of insulating films provided for the respective interconnect layers, each said insulating film being in contact with the respective wires belonging to the same one of the interconnect layers and laterally connecting the wires to each other; and an opening provided to pass through at least the uppermost one of the insulating films. Regions immediately under each said insulating film, through which the opening is formed, form a gas layer, and regions overlying the regions immediately under each said insulating film and surrounding the wires and the plugs also form a gas layer.
In this structure, regions immediately under each said insulating film, through which the opening is formed, form a gas layer, and regions overlying the regions immediately under each said insulating film and surrounding the wires and the plugs also form a gas layer. Thus, while the semiconductor device is used normally, the semiconductor device has a so-called xe2x80x9cgas-dielectric interconnect structurexe2x80x9d in which the air having a relative dielectric constant of approximately 1 functions as an insulating film between adjacent wires. Since the opening is provided in this manner, the film, which is interposed between adjacent insulating films for forming gas layers, can be removed easily during the formation of a semiconductor device. Thus, it is no longer necessary to reduce the thickness of an insulating film to such a value as to make the film penetrate oxygen, as has conventionally been done. Accordingly, a thick insulating film can be formed. Consequently, not only wiring delay can be reduced as is specific to a gas-dielectric interconnect structure, but also the overall strength of the multilevel interconnect structure can be increased and the reliability of the structure can be improved. Moreover, since the opening is provided, the gas layer between adjacent wires can be an opened gas layer. Thus, the damage, which has conventionally been done on the respective members because of the expansion and compression of the gas layers during heating and cooling of a semiconductor device, can be reduced, thereby improving the reliability of the semiconductor device. In other words, the first object of the present invention is accomplished.
In one embodiment, a pair of said insulating films are preferably provided for each said interconnect layer so as to come into contact with the upper and lower surfaces of the wires in each said interconnect layer.
In such a case, the wires can be strongly interconnected to each other via the insulating film.
If another embodiment, coating insulating films may be further formed on exposed surfaces of the wires and the plugs.
In such a case, even if moisture or humidity permeates the gas layers during the operation of the semiconductor device, the electrical shortcircuit of the wires and the disconnection thereof owing to erosion can be prevented. As a result, an even more reliable interconnect structure can be obtained.
A second semiconductor device according to the present invention includes: a semiconductor substrate; a plurality of interconnect layers disposed at respectively different levels above the semiconductor substrate, each said interconnect layer including a plurality of wires; a plurality of plugs, each said plug vertically connecting an associated wire in one of the interconnect layers to the semiconductor substrate or vertically connecting a pair of wires to each other, the pair of wires belonging to two mutually different ones of the interconnect layers; a plurality of first insulating films provided for the respective interconnect layers, each said first insulating film being in contact with the respective wires belonging to the same one of the interconnect layers and laterally connecting the wires to each other; and an opening provided to pass through at least the uppermost one of the first insulating films. Regions immediately under each said insulating film, through which the opening is formed, and regions overlying the regions immediately under each said insulating film and surrounding the wires and the plugs are filled with a low-dielectric-constant film having a relative dielectric constant of 2.8 or less.
In this structure, regions immediately under each said insulating film, through which the opening is formed, and regions overlying the regions immediately under each said insulating film and surrounding the wires and the plugs are filled with a low-dielectric-constant film having a relative dielectric constant of 2.8 or less. Thus, such a structure has a higher strength than that of a gas-dielectric interconnect structure and can considerably reduce wiring delay. In addition, even though a low-dielectric-constant film, having generally low thermal resistance, is used as an insulating film between adjacent wires, an insulating material for the low-dielectric-constant film can be easily introduced through the opening. Thus, when an interconnect layer is formed, it is possible to take a procedure, in which a gas layer is formed first and then a low-dielectric-constant material is introduced into the gas layer. That is to say, before the gas layers are formed, this structure can be subjected to a heat treatment or the like without being limited by the thermal resistance of the low-dielectric-constant film. Accordingly, wires having low resistance, made of a Cu alloy film, for example, can be provided.
A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a plurality of interconnect layers by sequentially stacking plugs and wires on a substrate, and forming an insulating film and a provisional film for each said interconnect layer, the insulating film laterally interconnecting the wires to each other, the provisional film filling in regions surrounding the plugs and the wires; b) forming an opening through at least the uppermost one of the insulating films and the uppermost one of the provisional films that are formed in the step a); and c) removing the provisional films while leaving the insulating films, thereby turning at least part of the regions where the provisional films existed into gas layers.
In accordance with this method, since the opening can be provided in the step b), gas or liquid for removing the provisional films can be introduced easily through the opening in the step c). The gas, liquid or the like used for the removal process can also be easily exhausted through the opening. Thus, unlike a conventional method for forming a gas-dielectric interconnect structure, it is no longer necessary to reduce the thickness of an insulating film to such a value as to make the film penetrate oxygen. As a result, it is possible to fabricate a semiconductor device having wires that are strongly interconnected via thick insulating films. In addition, since the provisional films can be removed by performing only one step, the number of process steps can be reduced. As a result, a semiconductor device having a gas-dielectric interconnect structure can be fabricated at a lower cost.
In one embodiment, the step a) may be performed by repeating several times the sub-steps of: i) forming a first provisional film on the substrate; ii) forming through holes in the first provisional film; iii) forming the plugs out of a conductive material to fill in the through holes; iv) forming a second provisional film over the substrate after the sub-step iii) has been performed; v) forming trenches having a wiring pattern in the second provisional film; vi) forming the wires out of a conductive material to fill in the trenches; and vii) forming an insulating film over the substrate after the sub-step vi) has been performed.
In accordance with this method, a gas-dielectric interconnect structure can be obtained by utilizing a trenched interconnect structure to be formed by a so-called xe2x80x9csingle-damascene processxe2x80x9d.
In another embodiment, the step a) may be performed by repeating several times the sub-steps of: i) forming a provisional film over a semiconductor substrate; ii) forming trenches and through holes in the provisional film, each said through hole extending downward from the bottom of an associated one of the trenches and passing through the provisional film; iii) forming the wires out of a conductive material to fill in the trenches and the plugs out of the conductive material to fill in the through holes; and iv) forming an insulating film over the substrate so as to come into contact with the wires after the sub-step iii) has been performed.
In accordance with this method, a gas-dielectric interconnect structure including trench-filling wires can be formed by performing simpler process steps utilizing a so-called xe2x80x9cdual-damascene processxe2x80x9d.
In still another embodiment, the step a) may be performed by repeating several times the sub-steps of: i) forming a provisional film over a semiconductor substrate; ii) forming through holes in the provisional film; iii) forming the plugs out of a conductive material to fill in the through holes, and the wires to be connected to the plugs and to extend upward through the provisional film; and iv) forming an insulating film over the substrate between the sub-steps i) and ii) and/or after the sub-step iii) has been performed.
In accordance with this method, a semiconductor device having a gas-dielectric interconnect structure can be obtained by utilizing the multilevel interconnects formed by etching and patterning processes generally employed.
In still another embodiment, in the step a), a carbon film is preferably formed as the provisional film, and in the step c), the carbon film is preferably removed by ashing with oxygen.
In still another embodiment, the step a) further includes the sub-step of forming an intermediate insulating film in the middle of the provisional film, the intermediate insulating film functioning as an etching stopper for forming the trenches. In such a case, the accuracy of the resulting wiring pattern can be improved.
In still another embodiment, in the step a), the provisional film may be made of a material having a high etch selectivity with respect to the insulating film, and in the step c), the provisional film may be removed by isotropic etching.
In still another embodiment, the method may further include the step of forming a coating insulating film on exposed surfaces of the wires and the plugs by introducing an insulating material into the gas layers through at least the opening after the step c) has been performed.
In such a case, it is possible to fabricate a semiconductor device, in which electrical shortcircuit between conductive regions exposed in the gas layer and the disconnection thereof can be prevented with more certainty.
In still another embodiment, the method may further include the step of forming a low-dielectric-constant film by introducing an insulating material into the gas layers through at least the opening and thereby filling in the gas layers with a material having a lower dielectric constant than that of the insulating film, after the step c) has been performed.
In such an embodiment, the method preferably further includes the step of connecting bonding wires to the wires in the uppermost one of the interconnect layers after the step c) has been performed and before the step of forming the low-dielectric-constant film is performed. In the step of forming the low-dielectric-constant film, the low-dielectric-constant film is preferably formed so as to cover connection portions between the wires in the uppermost interconnect layer and the bonding wires.